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AZ100LVEL16VT
ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable FEATURES
* * * * * * * High Bandwidth for 1GHz Similar Operation as AZ100LVEL16VR except in Disabled Condition: QHG is High Operating Range of 3.0V to 5.5V Minimizes External Components Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Available in a 3x3 mm or 2x2 mm MLP Package S-Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website PACKAGE
MLP 8 (2x2x0.75) MLP 8 (2x2x0.75) RoHS Compliant / Lead (Pb) Free MLP 8 (2x2x0.75) MLP 8 (2x2x0.75) RoHS Compliant / Lead (Pb) Free MLP 8 (2x2x0.75) MLP 8 (2x2x0.75) RoHS Compliant / Lead (Pb) Free MLP 8 (2x2x0.75) MLP 8 (2x2x0.75) RoHS Compliant / Lead (Pb) Free MLP 16 (3x3) MLP 16 (3x3) RoHS Compliant / Lead (Pb) Free DIE
1 2 3 4 5 6
PACKAGE AVAILABILITY PART NUMBER
AZ100LVEL16VTNA AZ100LVEL16VTNA+ AZ100LVEL16VTNB AZ100LVEL16VTNB+ AZ100LVEL16VTNC AZ100LVEL16VTNC+ AZ100LVEL16VTND AZ100LVEL16VTND+ AZ100LVEL16VTL AZ100LVEL16VTL+ AZ100LVEL16VTXP
MARKING
P9 P9+ P8 P8+ P2 P2+ P3 P3+ AZM 16T AZM+ 16T N/A
NOTES
1,2,3 1,2 1,2,4 1,2 1,2,5 1,2 1,2 1,2 1,2 1,2 6
DESCRIPTION
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: "Y" or "YY" for year followed by "WW" for week. Parts marked TNA for date codes prior to 4WW (prior to 2004). Parts marked TNB for date codes prior to 4WW (prior to 2004). Parts marked TNC for date codes prior to 4WW (prior to 2004). Waffle Pack
The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable. The QHG/QHG outputs have a voltage gain several times greater than the Q/Q outputs. MLP 16, 3x3 mm Package (VTL) or DIE (VTX) The AZ100LVEL16VTL and AZ100LVEL16VTX provide a selectable enable input (EN) that allows continuous oscillator operation. See truth table for the Enable function. If Enable pull-up is desired in the CMOS/TTL mode, an external 20 k resistor connecting EN to VCC will override the on-chip pull-down resistor. When disabled, the QHG output is forced high and the QHG output is forced low. The AZ100LVEL16VTL/VTX also provides a VBB and 470 internal bias resistors from D to VBB and D to VBB. The VBB pin can support 1.5 mA sink/source current. Bypassing VBB to ground with a 0.01 F capacitor is recommended. The outputs Q and Q each have a selectable on-chip pull-down current source. See truth table below for current source functions. External resistors may also be used to increase pull-down current to a maximum total of 25 mA. 1630 S. STAPLEY DR., SUITE 127 * MESA, ARIZONA 85204 * USA * (480) 962-5881 * FAX (480) 890-2541 www.azmicrotek.com
AZ100LVEL16VT
Outputs QHG and QHG each have an optional on-chip pull-down current source of 10 mA. When pad/pin VEEP is left open (NC), the output current sources are disabled and the QHG /QHG operate as standard PECL/ECL. When VEEP is connected to VEE, the current sources are activated. The QHG /QHG pull-down current can be decreased, by using a resistor to connect VEEP to VEE. (See graph on page 5.) MLP 8, 2x2 mm Package, VTNA, VTNB, VTNC & VTND Versions All MLP 8, 2x2mm versions of the AZ100LVEL16VT provide an enable input that allows continuous oscillator operation. VTNA and VTNB utilize an enable (EN) that operates in the PECL/ECL mode. When the EN input is LOW, the Q and QHG/QHG outputs follow the data inputs. When EN is HIGH, the QHG output is forced high and the QHG output is forced low. VTNC and VTND utilize an enable (EN) that operates in the CMOS/TTL mode. When the EN input is HIGH, the Q and QHG/QHG outputs follow the data inputs. When EN is LOW, the QHG output is forced high and the QHG output is forced low. For VTNA and VTND, both D and D inputs are brought out and tied to the VBB pin through 470 internal bias resistors. In VTNB and VTNC, the D input is internally tied directly to the VBB pin and the D input is tied to the VBB pin through a 470 internal bias resistor. Bypassing VBB to ground with a 0.01 F capacitor is recommended. All MLP 8, 2x2mm versions (VTNA, VTNB, VTNC & VTND) have the Q, QHG, and QHG current sources disabled, while the Q output operates with a 4 mA current source to VEE. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
ENABLE TRUTH TABLE MLP 16 (VTL) or DIE (VTX) EN-SEL EN Q/Q QHG NC PECL Low, VEE or NC Data Data NC PECL High or VCC Data High VEE* Data High CMOS Low or VEE VEE* CMOS High or VCC Data Data Data High VEE* NC, no external pull-up Data Data VEE* NC, with 20k to VCC *Connections to VCC or VEE must be less than 1. PIN DESCRIPTION PIN D/D Q/Q QHG/QHG VBB EN-SEL EN/EN CS-SEL VEEP VEE VCC FUNCTION Data Inputs Data Outputs Data Outputs w/High Gain Reference Voltage Output Selects Enable Logic Enable Input Selects Q and Q Current Source Magnitude Optional QHG and QHG Current Sources Negative Supply Positive Supply QHG Data Low Low Data Low Data
4mA EA.
Q Q D D
470 470
CS-SEL QHG QHG
10mA EA.
VBB
EN CMOS / TTL THRESHOLD MLP 16 (VTL) or DIE (VTX)
VEEP VEE EN-SEL
CURRENT SOURCE TRUTH TABLE MLP 16 (VTL) or DIE (VTX) CS-SEL Q Q NC 4mA typ. 4mA typ. VEE* 8mA typ. 8mA typ. VCC* 0 4mA typ. *Connections to VCC or VEE must be less than 1.
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AZ100LVEL16VT
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol VCC VI VEE VI IOUT TA TSTG Characteristic PECL Power Supply (VEE = 0V) PECL Input Voltage (VEE = 0V) ECL Power Supply (VCC = 0V) ECL Input Voltage (VCC = 0V) Output Current QHG/QHG --- Continuous --- Surge Q/Q --- Continuous Output Current --- Surge Operating Temperature Range Storage Temperature Range Rating 0 to +8.0 0 to +6.0 -8.0 to 0 -6.0 to 0 50 100 25 50 -40 to +85 -65 to +150 Unit Vdc Vdc Vdc Vdc mA C C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol VOH VOH VOL VIH VIL VBB IIL IIH IEE 1. 2. 3. 4. Characteristic
2
-40C Min -1045 -1085 -1925 Max -835 -880 -1555 Min -995 -1025 -1900
0C Max -835 -880 -1620 Min -995 -1025 -1900
25C Max -835 -880 -1620 Min -995 -1025 -1900
85C Max -835 -880 -1620 -880 VCC -1475 VEE + 800 -1250 150 54
Unit mV mV mV mV mV mV A A mA
Output HIGH Voltage Output HIGH Voltage4 Output LOW Voltage2,4 Input HIGH Voltage -880 -880 -1165 -880 D/D, EN/EN (PECL) -1165 -1165 VCC VCC VEE+2000 VCC EN (CMOS/TTL) VEE+2000 VEE+2000 Input LOW Voltage -1475 -1810 -1475 -1810 -1475 D/D, EN/EN (PECL) -1810 VEE + 800 VEE VEE + 800 VEE VEE + 800 EN (CMOS/TTL) VEE Reference Voltage -1390 -1250 -1390 -1250 -1390 -1250 Input LOW Current EN3 0.5 0.5 0.5 Input HIGH Current EN3 150 150 150 Power Supply Current1 48 48 48 Specified with VEEP and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND. Specified with VEEP and CS-SEL connected to VEE for VTL and VTX only. Specified with EN-SEL open for VTL and VTX only. Specified with QHG/QHG connected with 50 to VCC -2V for VTNA, VTNB, VTNC & VTND.
-1165 VEE+2000 -1810 VEE -1390 0.5
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol VOH VOH VOL VIH VIL VBB IIL IIH IEE 1. 2. 3. 4. 5. Characteristic
1,3
-40C Min 2255 2215 1375 Max 2465 2420 1745 Min 2305 2275 1400
0C Max 2465 2420 1655 Min 2305 2275 1480
25C Max 2465 2420 1680 Min 2305 2275 1400 2135 2000 1490 GND 1910 0.5
85C Max 2465 2420 1680 2420 VCC 1825 800 2050 150 54
Unit mV mV mV mV mV mV A A mA
Output HIGH Voltage Output HIGH Voltage1,5 Output LOW Voltage1,3,5 Input HIGH Voltage 2135 2420 2135 2420 2135 2420 D/D, EN/EN (PECL)1 EN (CMOS/TTL) 2000 VCC 2000 VCC 2000 VCC Input LOW Voltage 1490 1825 1490 1825 1490 1825 D/D, EN/EN (PECL)1 EN (CMOS/TTL) GND 800 GND 800 GND 800 Reference Voltage1 1910 2050 1910 2050 1910 2050 Input LOW Current EN4 0.5 0.5 0.5 Input HIGH Current EN4 150 150 150 Power Supply Current2 48 48 48 For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value. Specified with VEEP and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND. Specified with VEEP and CS-SEL connected to VEE for VTL and VTX only. Specified with EN-SEL open for VTL and VTX only. Specified with QHG/QHG connected with 50 to VCC -2V for VTNA, VTNB, VTNC & VTND.
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AZ100LVEL16VT
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol VOH VOH VOL VIH VIL VBB IIL IIH IEE 1. 2. 3. 4. 5. Characteristic
1,3
-40C Min 3955 3915 3075 Max 4165 4120 3445 Min 4005 3975 3100
0C Max 4165 4120 3338 Min 4005 3975 3100
25C Max 4165 4120 3338 Min 4005 3975 3100 3835 2000 3190 GND 3610 0.5
85C Max 4165 4120 3338 4120 VCC 3525 800 3750 150 54
Unit mV mV mV mV mV mV A A mA
Output HIGH Voltage Output HIGH Voltage1,5 Output LOW Voltage1,3,5 Input HIGH Voltage 3835 4120 3835 4120 3835 4120 D/D, EN/EN (PECL)1 EN (CMOS/TTL) 2000 VCC 2000 VCC 2000 VCC Input LOW Voltage 3190 3525 3190 3525 3190 3525 D/D, EN/EN (PECL)1 EN (CMOS/TTL) GND 800 GND 800 GND 800 1 Reference Voltage 3610 3750 3610 3750 3610 3750 Input LOW Current EN4 0.5 0.5 0.5 Input HIGH Current EN4 150 150 150 Power Supply Current2 48 48 48 For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value. Specified with VEEP and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND. Specified with VEEP and CS-SEL connected to VEE for VTL and VTX only. Specified with EN-SEL open for VTL and VTX only. Specified with QHG/QHG connected with 50 to VCC -2V for VTNA, VTNB, VTNC & VTND.
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
Max Propagation Delay tPLH / tPHL 400 400 400 430 (SE) D to Q/Q Outputs1 550 550 550 630 D to QHG/QHG Outputs1 (SE) tSKEW Duty Cycle Skew2 (SE) 5 20 5 20 5 20 5 20 80 80 80 80 Minimum Input Swing3 DIFF VPP SE 160 160 160 160 Output Rise/Fall Times1 100 260 100 260 100 260 100 260 tr / t f (20% - 80%) 1. For VTL and VTX, output specified with VEEP and CS-SEL connected to VEE with an AC coupled 50 load. For VTNA, VTNB, VTNC & VTND, AC coupled 50 on Q to VCC -2V and DC coupled 50 to VCC -2V on QHG/QHG. 2. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 3. VPP is the minimum peak-to-peak input swing for which AC parameters guaranteed. The device has a voltage gain of 20 to Q/Q outputs and a voltage gain of 100 to QHG/QHG outputs. Symbol Characteristic Min -40C Typ Max Min 0C Typ Max Min 25C Typ Max Min 85C Typ Unit ps ps mV ps
D EN EN
(VTL, VTX);
EN
(VTNA, VTNB)
(PECL) (CMOS)
(VTL, VTX, VTNC, VTND)
Q Q Q HG Q HG TIMING DIAGRAM
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AZ100LVEL16VT
AZ100LVEL16VTL
MLP 16 3x3 mm
Q 16 NC D D VBB 1 2 3 4 5 EN 6 NC 7 VEE 8 VEEP Q 15 NC 14 VCC 13 12 CS-SEL 11 QHG
10 QHG 9 EN-SEL
TOP VIEW
Bottom Center Pad may be left open or tied to VEE
ADJUSTABLE HIGH GAIN OUTPUT CURRENT
12 HIGH GAIN OUTPUT CURRENTS (mA) 10 8 6 4 2 0 0 20 40 60 80 100 120 140 160 180 200 VEEP TO VEE RESISTOR VALUE (OHMS)
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AZ100LVEL16VT
1.2
0
1.1
-15
1
-30
Magnitude
0.9
-45
S11 MAG 8mA S11 MAG 4mA S11 PHASE 8mA S11 PHASE 4mA
0.8
-60
0.7
-75
0.6 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
-90
Frequency (MHz)
(50 external AC, 4 & 8mA internal DC Load on Q)
0.05 195
S11, D to Q
0.04
170
0.03
145 S12 MAG 8mA S12 MAG 4mA S12 PHASE 8mA S12 PHASE 4mA
Magnitude
0.02
120
0.01
95
0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
70
Frequency (MHz)
(50 external AC, 4 & 8mA internal DC Load on Q)
S12, D to Q
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Phase
Phase
AZ100LVEL16VT
45
195
40
165
35
135
30
105
Magnitude
Phase
25
75
S21 MAG 8mA S21 MAG 4mA S21 PHASE 8mA S21 PHASE 4mA
20
45
15
15
10
-15
5
-45
0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
-75
Frequency (MHz)
(50 external AC, 4 & 8mA internal DC Load on Q)
S21, D to Q
0.9
225
0.8
200
0.7
175 S22 MAG 8mA S22 MAG 4mA S22 PHASE 8mA S22 PHASE 4mA
Magnitude
0.6
150
0.5
125
0.4 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
100
Frequency (MHz)
(50 external AC, 4 & 8mA internal DC Load on Q)
S22, D to Q
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Phase
AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
4mA
Q D D
470 470
MLP 8, 2x2mm
V EE Q HG Q HG
D D
1 2
AZ100LVEL16VTNA
8 7
Q VCC QHG QHG
V BB EN
VEE VBB 3 6 5 TOP VIEW
MLP 8, 2x2mm AZ100LVEL16VTNA
4mA
EN
4
VEE operation follows PECL functionality. EN D QHG See Timing Diagram above. 470 QHG VBB EN
Q
Bottom1Center Pad is the VEE 8 Q AZ100LVEL16VTNB return. D
VBB EN VEE 2 3 4 7 6 5 VCC QHG QHG
MLP 8, 2x2mm
MLP 8, 2x2mm AZ100LVEL16VTNB
TOP VIEW
operation follows PECL functionality. EN See Timing Diagram above.
Bottom Center Pad may be left open or tied to VEE. Pin 4 is the VEE return.
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AZ100LVEL16VT LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
4mA
Q D
470
MLP 8, 2x2mm
V EE Q HG Q HG
D VBB EN VEE
1 2 3 4
AZ100LVEL16VTNC 8 7 6 5
Q VCC QHG QHG
V BB EN
CMOS / TTL THRESHOLD
MLP 8, 2x2mm AZ100LVEL16VTNC
TOP VIEW
EN operation follows CMOS/TTL functionality. See Timing Diagram above.
Bottom Center Pad may be left open or tied to VEE. Pin 4 is the VEE return.
4mA
MLP 8, 2x2mm
V EE Q HG Q HG
Q D D V BB EN
470 470
D D
1 2
AZ100LVEL16VTND
8 7
Q VCC QHG QHG
VEE 6 5 TOP VIEW
VBB 3 EN 4
CMOS / TTL THRESHOLD
MLP 8, 2x2mm AZ100LVEL16VTND
EN operation follows CMOS/TTL functionality. See Timing Diagram above.
Bottom Center Pad is the VEE return.
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AZ100LVEL16VT
DIE PAD COORDINATES
AZ100LVEL16VT DIE:
LV16VT
A B C D
M
L
K J
DIE SIZE: 950u X 950u DIE THICKNESS: 14 MILS BOND PAD: 85u X 85u
I H G
E
F
PAD CENTER COORDINATES NAME A B C D E F G H I J K L M PAD DESIGNATION D D VBB EN VEE VEEP EN-SEL QHG QHG CS-SEL VCC Q Q X(Microns) -342.5 -342.5 -342.5 -342.5 -33.5 126.5 312.5 312.5 312.5 312.5 302.5 142.5 -140.5 Y(Microns) 312.5 144.5 -87.0 -255.0 -312.5 -312.5 -248.5 -98.5 51.5 201.5 342.5 342.5 342.5
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AZ100LVEL16VT PACKAGE DIAGRAM MLP 8 2x2mm
Pin 1 Dot By Marking 2.0000.050
2.0000.050
MLP 8 (2x2mm)
TOP VIEW
0.3500.050 0.2500.050 8 7 0.500 bsc 6 5 1
Pin 1 Identification R0.100 TYP
2 1.2000.050 exp. pad 3 4 0.6000.050 exp. pad
BOTTOM VIEW
1.750 Ref.
0.7500.050 0.000-0.050
1
2
34 0.2030.025
SIDE VIEW
Note: All dimensions are in mm
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AZ100LVEL16VT
PACKAGE DIAGRAM MLP 16 3X3mm
D
2. INDEX AREA (D/2 x E/2)
A D 2 E 2 E
3x e e
B
D2 D2/2 E2/2 E2
2 1
5.
2x 2x
aaa C aaa C TOP VIEW bbb M C A B
16 x b 3. 3x e BOTTOM VIEW
L
ccc C
A
4. 0.08 C SIDE VIEW
A3 C SEATING PLANE
A1
NOTES: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME T14-1994. 2. THE TERMINAL #1 AND PAD NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. 3. DIMENSION b APPLIES TO METALLIZED PAD AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM PAD TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. 5. INSIDE CORNERS OF METALLIZED PAD MAY BE SQUARE OR ROUNDED
MILLIMETERS DIM A A1 A3 b D D2 E E2 e L aaa bbb ccc MIN MAX 0.80 1.00 0.05 0.00 0.25 REF 0.18 0.30 3.10 2.90 1.95 0.25 3.10 2.90 1.95 0.25 0.50 BSC 0.30 0.50 0.25 0.10 0.10
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AZ100LVEL16VT
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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